CPC Guide - The Gate ArrayGate Array Introduction The gate array is a specially designed chip exclusively for use in the Amstrad CPC. It is for this reason not much is known about it, however from extensive research I have managed to compile the information in this document. It was designed by Amstrad. It is responsible for controlling screen mode, colour palette, ram configuration and rom configuration. The "new" ASIC Gate Array (in the new Plus machines) is described here. In standard mode on the Plus machines (that is when the new ASIC Gate Array has not been enabled), it acts as a standard gate array, allowing programs on the CPC to work on the Plus machines without modification. However when the new ASIC gate array is enabled, it allows the user to use some extra enhancements. The Gate Array is described here, as it would be on a standard CPC. What does it do? Gate Array pin-outs Controlling the gate array Pen selection Colour selection Mode Selection Expansion ROM enable/disable Operating System ROM enable/disable Ram configuration Programming examples Conversion chart for firmare to hardware colour number Colour Generation by RGB mixing Green screen colours What does it do? The gate array is resposible for many things inside the CPC. Display The CRTC reads data from the CPC memory and passes it to the gate array which interprets the data depending on the current mode selected, and then adds colour depending on the current palette settings. This data is converted into red, green and blue components which are sent to the monitor. The gate array recieves some signals from the CRTC to help it to build the display. DISPTMG when low tells the gate array to interpret the data as pixels, and when high tells the gate array to ignore the data and put border colour. HSYNC The gate array will only allow a mode change when a HSYNC occurs. The new mode is stored until the HSYNC is received and then the mode is changed, this has probably been built into the hardware because there might be some graphics distortion if the mode change was visible. This is also passed to the monitor to maintain a steady image. VSYNC This is passed to the monitor to maintain a steady image. Interrupts The interrupts originate from the gate array. Every 1/300th of a second the gate array will send the interrupt pulse to the z80 and wait for an acknowledgement. If the z80 has interrupts enabled, they will be processed almost immediatly, otherwise the interrupt is held. Pin connections of the Gate Array The Gate Array has a number on the top and this defines it's "version". The pin-outs of each version are different. Here are the pin connections and their functions as I understand them. Gate Array 40007/40008 40007 used in CPC464. This became so hot it need a heat sink (piece of aluminium) to keep it cool. 40008 used in CPC664. No heat sink required. With some old CPC6128 there is space on the curcuit board to put a 40007/40008. _________________________ /CPU ADDR -|1 |- MA0/CCLK READY -| |- 0 /CAS -| |- Vcc1 /244EN -| |- /RESET /MWE -| |- R /CAS ADDR -| |- Gnd /RAS -| |- G XTAL -| |- Vcc2 Vcc2 -| |- B /INTERRUPT-| |- D7 /SYNC -| |- D6 /ROMEN -| |- D5 /RAMRD -| |- D4 HSYNC -| |- D3 VSYNC -| |- D2 /IORQ -| |- D1 /M1 -| |- D0 /MREQ -| |- DISPEN /RD -| |- Vcc1 A15 -|_________________________|- A14 Gate Array 40010 40010 used in CPC6128. _________________________ D5 -|1 |- D4 D6 -| |- D3 D7 -| |- D2 CCLK -| |- D1 /SYNC -| |- Vss Vdd -| |- D0 /RESET -| |- /RAS R -| |- /MWE DISPEN -| |- /INT G -| |- /CAS ADDR HSYNC -| |- A14 R -| |- /RAMRD VSYNC -| |- A15 /CPU -| |- /ROMEN Vss -| |- Vss /CAS -| |- Vdd MREQ -| |- CK16 /IORQ -| |- /244EN 0 -| |- READY /NMI -|_________________________|- /RD Pin Descriptions This is a description of the Gate Array pins as I understand them. R,G,B = Analogue colour information for each pixel XTAL = 16Mhz clock for the Gate Array D0-D7 = Data (upper two bits are used to define function performed by gate array) A15 & A14 = These are used to identify the memory block being accessed. Therefore the Gate array can decide if RAM or ROM is to be accessed and act accordingly. It can also be used to identify if the Gate Array functions are being accessed by the CPU. VSYNC & HSYNC = these come from the CRTC and give the Gate array knowledge about the status of the display. The HSYNC is probably used as a counter to trigger interrupts. These are both mixed to a composite sync that is fed to the monitor. DISPEN = comes from CRTC. Used to determine when graphics is displayed and when border starts and ends. /ROMEN = goes low when processor address is within an area that can be occupied by a ROM, and when the ROM is enabled for that area. /RAMRD = goes low when processor address is within an area that is RAM or could be ROM, but ROM disabled for that area. /SYNC = composite sync output to the monitor /IORQ = low if the processor is performing access to hardware elements. OUT command or IN command. This is probably used in conjunction with D0-D7 and A15/A14 to identify a OUT command intended for the Gate Array and the data to be processed. It may be possible that the decoding logic which is normally required to select the chip is inside the gate array. I dont know without looking inside. Therefore it is possible the Gate array performs it's own address decoding to decide if it needs the information. It is true that with an OUT command, A15 is low for a gate array write (check this) /RESET = normal input used to reset chip status (reset switch or when turned off and then on) Input The Z80 data bus is not connected to data lines d0-d7, but via a data bus buffer. /244EN goes low when a port address of &7fxx is recognised and /IORQ is present so that the data can be fed to the Gate Array. /IORQ & /M1 are set to low when an interrupt is acknowledged by the CPC. Therefore the gate array uses this to clear the interrupt. These are input. /INTERRUPT - This is output, connected to CPU interrupt request pin. A memory write always goes to RAM. The Gate array generates a /MWE for any memory write. Output. MA0/CCLK = supplied to CRTC. Used to get 2 data bytes per memory fetch. See these docs for more info. Also used as clock for CRTC. /CPUADDR = low when CPU is accessing memory. Also used as clock for CRTC and Sound chip. 0 (Phi) = 4Mhz clock for Z80. /CAS ADDR,/CAS,/RAS all to do with some kind of timing for accessing ram by CRTC when Z80 not using it etc. Controlling the Gate Array The gate array is controlled by sending values to port &7Fxx. The function which is to be performed is dependant on the settings of bits 7 and 6; the remaining bits are data used by the appropiate function. All these registers are write only and cannot be read. A brief description of the functions are described below with their settings for bit 7 and 6. Bit 7 Bit 6 Function ------------------------ 0 0 Select which pen is to have its colour changed. 0 1 Select colour for currently selected pen. (from hardware colour palette) 1 0 Select screen mode and rom configuration. 1 1 Select ram configuration (bank switching). Pen selection When bit 7 and bit 6 are set to 0, the remaining bits determine which pen is to have its colour changed. Bits 3 to 0 define which pen is to be selected. When bit 4 is set to 1, the value contained in bits 3-0 is ignored and the border is selected. The pen remains selected until another is selected. Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens. Summary Bit 7: } Gate Array function (0) Bit 6: } (0) Bit 5: Not used Bit 4: Border selection 1=Select border, 0=use pen value contained in bits 3-0. Bit 3: } Pen number Bit 2: } Bit 1: } Bit 0: } Colour selection Once the pen has been selected the colour can then be changed. Bits 4 to 0 hold the colour number (from the hardware pallette). The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name. Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette. Note: The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to it's original colour. This is due to the firmware re- setting the colour. When using the firmware, use it's routines to select the colour, and the colour will remain. Summary Bit 7: } Gate Array function (0) Bit 6: } (1) Bit 5: Not used. Bit 4: } Colour number (from hardware colour palette) Bit 3: } Bit 2: } Bit 1: } Bit 0: } Select screen mode and rom configuration This is a general purpose register responsible for the screen mode and the rom configuration. Screen mode selection The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. This mode may be different on different versions of the Gate Array and on different CPC models. The screen mode is changed when a HSYNC occurs. Bit 1 Bit 0 Screen mode ----------------------------------- 0 0 Mode 0,160x200, 16 colours. 0 1 Mode 1,320x200, 4 colours. 1 0 Mode 2,640x200, 2 colours 1 1 Mode 3,160x200, 4 colours. Rom configuration selection (See the memory map for more information) Bit 2 is used to enable or disable the lower rom. The lower rom occupies memory addressess &0000-&3fff. When it is enabled, reading from &0000-&3FFF will return data in the rom. When a value is written to &0000-&3FFF, it will be written to the ram at the same address as the rom. When it is disabled, data read from &0000-&3FFF will return the data in the ram. Similarly, bit 3 controls enabling or disabling of the upper rom. The upper rom resides in memory addressess &C000-&FFFF. The upper rom can be basic or any other extra expansion roms which may be plugged into an expansion board. The upper rom is selected by writing the rom number to port &DFxx. (See upper rom selection for more information). When the upper rom is enabled, reading from &c000-&ffff, will return data in the rom. When data is written to &c000-&FFFF, it will be written to the ram at the same address as the rom. When the upper rom is disabled, and data is read from &c000-&ffff the data returned will be the data in the ram. Bit 4 controls the CPU interrupts. A CPU interrupt occurs every 300th of a second. When an interrupt occurs, the CPU stops executing the current program, and executes an interrupt program. When the interrupt program has been completed, it returns to the current program. (See interrupts for more information). Bit 4 is used to control the timing of interrupts. When this bit is set to 1, any pending interrupts are cleared and the top bit of the scanline counter is cleared (this will suspend the next interrupt for a few scanlines). When this bit is set to 0, the next interrupt will continue as normal. See this document for more information. Summary Bit 7: } Gate Array function (1) Bit 6: } (0) Bit 5: Not used. Bit 4: CPU Interrupt enable/disable 1:disable next interrupt, 0:enable next interrupt Bit 3: Upper rom enable/disable. (Expansion roms) 1:disable upper rom, 0:enable upper rom Bit 2: Lower rom enable/disable. (Operating System rom) 1:disable lower rom, 0:enable lower rom Bit 1: } Screen Mode Bit 0: } Select ram configuration This register is used to select the ram configuration. The ram is split into banks of 64K. Each of these banks is split into blocks of 16K. Using this register, the user can select which bank they wish to use and how it is 'mixed' with the main ram. The CPU is capable of accessing a maximum of 64K at one time. To access extra memory, blocks in the main ram (bank 1) can be exchanged with blocks in the extra ram. The number of blocks exchanged and the the blocks they change place with changes depending on the ram configuration used. Ram configurations Bits 2-0 select which ram configuration is to be used. When configuration 0 is selected (regardless of the bank selected), the CPU will only access the main ram. When configuration 2 is selected the CPU will only access the bank selected. In the table above, 0-3 are the blocks in the main ram (bank 1), and 4-7 are the blocks of the selected bank, as they would normally be arranged shown below. Their new position, is the position they would take if that configuration was used. It is not adviseable to use configuration 2 when the firmware is running, or the computer will crash and you will lose valuable data. NOTE Normally the CPC runs in ram configuration 0 (AMSDOS) and configuration 1 (CP/M). The CRTC can only display graphics from the main ram. The Amstrad hardware was designed, so that it could not use the additional memory to store graphics. Normal arrangement of blocks: (Without any ram configuration selected). Main Ram Selected bank (bank 1) &FFFF +---------------+---------------+ | | | | 3 | 7 | | | | &C000 +---------------+---------------+ | | | | 2 | 6 | | | | &8000 +---------------+---------------+ | | | | 1 | 5 | | | | &4000 +---------------+---------------+ | | | | 0 | 4 | | | | &0000 +---------------+---------------+ Bit 2 Bit 1 Bit 0 Configuration number -------------------------------------------- 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Organization Block accessed at memory address &0000-&3FFF &4000-&7fff &8000-&bfff &c000-&ffff 0 0 1 2 3 1 0 1 2 7 2 4 5 6 7 3 0 3 2 7 4 0 4 2 3 5 0 5 2 3 6 0 6 2 3 7 0 7 2 3 Bank selections Bits 5-3 select the bank required as shown in the table below. Bit 5 Bit 4 Bit 3 Bank Selected --------------------------------------------- 0 0 0 Bank 2 0 0 1 Bank 3 0 1 0 Bank 4 0 1 1 Bank 5 1 0 0 Bank 6 1 0 1 Bank 7 1 1 0 Bank 8 1 1 1 Bank 9 NOTE: If you have 64k, and you attempt to use a bank and ram configuration, there will be no effect. i.e. the arrangement of the 64K will not change. If you only have 128k, regardless of the bank you choose, bank 2 will be selected. If you have more than 128K, you will be able to choose the bank and the ram configuration and it will arrange the ram correctly. Summary Bit 7:} Gate Array Function (1) Bit 6:} (1) Bit 5:} Bank Bit 4:} Bit 3:} Bit 2:} Ram configuration Bit 1:} Bit 0:} Programming the Gate Array - Examples 1) Defining the colours, Setting pen 0 to Bright White. LD BC,&7F00 ;Gate Array port LD A,%00000000+0 ;Pen number (and Gate Array function) OUT (C),A ;Send pen number LD A,%01000000+11 ;Pen colour (and Gate Array function) OUT (C),A ;Send it RET 2) Setting the mode and rom configuration, Mode 2, upper and lower rom disabled. LD BC,&7F00 ;Gate array port LD A,%10000000+%00001110 ;Mode and rom selection (and Gate ;Array function) OUT (C),A ;Send it RET 3) Setting the ram configuration, Setting configuration 1. LD BC,&7F00 ;Gate array port LD A,%11000000+%00000001 ;Ram configuration (and Gate Array ;function) OUT (C),A ;Send it RET Palette conversion chart Firmware colour Colour Hardware palette Quick number number Reference 0 Black 20 &54 1 Blue 4 &44 2 Bright Blue 21 &55 3 Red 28 &5C 4 Magenta 24 &58 5 Mauve 29 &5D 6 Bright Red 12 &4C 7 Purple 5 &45 8 Bright Magenta 13 &4D 9 Green 22 &56 10 Cyan 6 &46 11 Sky Blue 23 &57 12 Yellow 30 &5E 13 White 0 &40 14 Pastel Blue 31 &5F 15 Orange 14 &4E 16 Pink 7 &47 17 Pastel Magenta 15 &4F 18 Bright Green 18 &52 19 Sea Green 2 &42 20 Bright Cyan 19 &53 21 Lime 26 &5A 22 Pastel green 25 &59 23 Pastel Cyan 27 &5B 24 Bright Yellow 10 &4A 25 Pastel Yellow 3 &43 26 Bright White 11 &4B This chart also gives a quick reference guide for programming the colours. The number is the colour number which can be sent directly, once the pen has been selected, to get the colour wanted. Example: ld bc,&7f00+1 ;Gate array function (set pen) ;and pen number out (c),c ld bc,&7f00+&41 ;Gate array function (set colour) ;and colour number out (c),c ret Pallette R,G,B definitions for emulators There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour. To display a CPC image you will need to use a analogue monitor with a composite sync. This table shows the relationship between hardware colour number, colour name and RGB mixing. (* indicates a colour which is a copy of a documented colour in the hardware colour palette) Hardware Colour name Red Green Blue colour (%) (%) (%) number 0 White 50 50 50 1 *White 50 50 50 2 Sea Green 0 100 50 3 Pastel yellow 100 100 50 4 Blue 0 0 50 5 Purple 100 0 50 6 Cyan 0 50 50 7 Pink 100 50 50 8 *Purple 100 0 50 9 *Pastel yellow 100 100 50 10 Bright yellow 100 100 0 11 Bright White 100 100 100 12 Bright red 100 0 0 13 Bright magenta 100 0 100 14 Orange 100 50 0 15 Pastel magenta 100 50 100 16 *Blue 0 0 50 17 *Sea green 0 100 50 18 Bright green 0 100 0 19 Bright cyan 0 100 100 20 Black 0 0 0 21 Bright Blue 0 0 100 22 Green 0 50 0 23 Sky Blue 0 50 100 24 Magenta 50 0 50 25 Pastel Green 50 100 50 26 Lime 50 100 0 27 Pastel Cyan 50 100 100 28 Red 50 0 0 29 Mauve 50 0 100 30 Yellow 50 50 0 31 Pastel blue 50 50 100 RGB assignments for the software colours This is simply a sidenote to illustrate a pattern in the RGB assignments of the software colours and to show how their value is calculated. Firmware Colour Colour name R G B Number (%) (%) (%) 0 Black 0 0 0 1 Blue 0 0 50 2 Bright Blue 0 0 100 3 Red 50 0 0 4 Magenta 50 0 50 5 Mauve 50 0 100 6 Bright Red 100 0 0 7 Purple 100 0 50 8 Bright Magenta 100 0 100 9 Green 0 50 0 10 Cyan 0 50 50 11 Sky Blue 0 50 100 12 Yellow 50 50 0 13 White 50 50 50 14 Pastel Blue 50 50 100 15 Orange 100 50 0 16 Pink 100 50 50 17 Pastel Magenta 100 50 100 18 Bright Green 0 100 0 19 Sea Green 0 100 50 20 Bright Cyan 0 100 100 21 Lime 50 100 0 22 Pastel Green 50 100 50 23 Pastel Cyan 50 100 100 24 Bright Yellow 100 100 0 25 Pastel Yellow 100 100 50 26 Bright White 100 100 100 To calculate the colour value: Red 0% => do not add anything 50% => add 3 100% => add 6 Green 0% => do not add anything 50% => add 9 100% => add 18 Blue 0% => do not add anything 50% => add 1 100% => add 2 Green Screen Colours On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. So that black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to Mark Rison for suggesting I add this).