CPC Guide - Interrupts revisitedInterrupts Revisited - Interrupts 2 Article supplied by Brice Rive The main reason for the interrupt delay mechanism is to allow for discrimination between Gate Array interrupts and external interrupts (from the extension port): The mechanism implemented by Locomotive to distinguish between GA Ints and external Ints is as follows: When the Z80 is in enabled interrupts and notices a low level on the INT line, it disables interrupts and jumps to address 0x0038. At the same time, it puts lines IORQ and M1 to 0. This is recognized as an interrupt acknoledge by the GA, which in turn sets its output INT line back to 1. The interrupt routine starts with: 0038 JP B941 B941 DI EX AF,AF' JR C,B978 EXX LD A,C SCF ---> EI EX AF,AF' DI ... The Z80, shortly after being interrupted will briefly re-enable interrupts (EI). In the case of a GA Int, this has no effect because the GA has already reset its INT line to 1. In the case of an external Int however, the INT line will still be at 0, and the code will be re-interrupted. This situation will be detected by the fact that AF' CARRY flag was set, and the interrupt routine will jump to B978 where the external interrupt handling code is located. So the key to this mechanism is that, when the Z80 executes EI, the INT line is at 1 for a GA Int and at 0 for an external Int. This means that external interrupts must be long enough, and that the GA interrupt line must be low by thsat time. However, without the interrupt delay mechanism, there could be a situation where the GA's scan counter reaches 52 again just when the Z80 executes EI (if the Z80 ignored the first interrupt long enough by running in interrupt disabled mode). This would be wrongly interpreted as an external interrupt and ... BOUM! To prevent that, when the GA detects the interrupt acknowledge from the Z80, it also resets the high bit of its scan counter. This is a kludgy but efficient way to avoid the race condition described above. Brice.